Universidad Antonio de Nebrija

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The following papers have been produced based on our research work:

Book Chapters

P. Reviriego, J.A. Maestro, "Soft Errors in Digital Circuits: Overview and Protection Techniques for Digital Filters", in "Radiation Effects in Semiconductors" (ISBN: 978-1-4398-2694-2), CRC Press, Ed. Kris Iniewski, August 2010, pp. 357-384.

IEEE/ACM Journals in JCR
See copyright note at the end of this page

P. Reviriego, M. Flanagan, S. Liu, J.A. Maestro, "On the Use of Euclidean Geometry Codes for Efficient Multibit Error Correction on Memory Systems", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), 2012 (in press).
P. Reviriego, M. Flanagan, S. Liu, J.A. Maestro, "Error-Detection Enhanced Decoding of Difference Set Codes for Memory Applications", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), 2012 (in press).
P. Reviriego, J.A. Maestro, M. Flanagan, "Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), 2012 (in press).
P. Reviriego, M. Flanagan, J.A. Maestro, "A (64,45) Triple Error Correction Code for Memory Applications", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), 2012 (in press).
S. Liu, P. Reviriego, J.A. Maestro, "Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 20, No 1, January 2012, pp. 148-156.
J.A. Maestro, P. Reviriego, S. Baeg, S. Wen, R. Wong, "Mitigating the Effects of Large Multiple Cell Upsets (MCUs) in Memories”, ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 16, No 4, October 2011, pp. 45:1-45:10.
P. Reviriego, C. Bleakley, J.A. Maestro, A. O’Donnell, "Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform Based Convolution", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 60, No 10, October 2011, pp. 1511-1516.
P. Reviriego, C. Bleakley, J.A. Maestro, "Structural DMR: a Technique for Implementation of Soft Error Tolerant FIR Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 58, No 8, August 2011, pp. 512-516.
M. Ajmone-Marsan, A. Fernández-Anta, V. Mancuso, B. Rengarajan, P. Reviriego, G. Rizzo, "A Simple Analytical Model for Energy Efficient Ethernet”, IEEE Communications Letters (ISSN: 1089-7798), Vol. 15, No 7, July 2011, pp. 773-775.
P. Reviriego, C. Argyrides, J.A. Maestro, D.K. Pradhan, "Improving Memory Reliability against Soft Errors Using Block Parity", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 58, No 3, June 2011, pp. 981-986.
S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J.A. Maestro, M. Alderighi, "Increasing Reliability of FPGA-based Adaptive Equalizers in the Presence of Single Event Upsets", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 58, No 3, June 2011, pp. 1072-1077.
P. Reviriego, K. Christensen, J. Rabanillo, J.A. Maestro, "An Initial Evaluation of Energy Efficient Ethernet", IEEE Communications Letters (ISSN: 1089-7798), Vol. 15, No 5, May 2011, pp. 578-580.
P. Reviriego, B. Huiszoon, V. López, R.B. Coenen, J.A. Hernández, J.A. Maestro, "Improving Energy Efficiency in IEEE 802.3ba High-Rate Ethernet Optical Links", IEEE Journal of Selected Topics in Quantum Electronics (ISSN 1077-260X), Vol. 17, No 2, March/April 2011, pp. 419-427.
K. Christensen, P. Reviriego, B. Nordman, M. Bennett, M. Mostowfi, J. A. Maestro, "IEEE 802.3az: The Road to Energy Efficient Ethernet", IEEE Communications Magazine (ISSN: 0163-6804), Vol. 48, No 11, November 2010, pp. 50-56.
P. Reviriego, L. Holst, J.A. Maestro, "Number of Events and Time to Failure Distributions for Error Correction Protected Memories", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 10, No 3, September 2010, pp. 381-389.
P. Reviriego, J.A. Maestro, S. Liu, "Efficient Soft Error-Tolerant Adaptive Equalizers", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 57, No 8, August 2010, pp. 2032-2040.
C. Argyrides, P. Reviriego, D.K. Pradhan, J.A. Maestro, "Matrix-Based Codes for Adjacent Error Correction", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2106-2111.
S. Liu, P. Reviriego, J.A. Maestro, "Enhanced Implementations of Hamming Codes to Protect FIR Filters", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2112-2118.
P. Reviriego, J.A. Maestro, S. Baeg, S. Wen, R. Wong, "Protection of Memories Suffering MCUs through the Selection of the Optimal Interleaving Distance", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2124-2128.
J.A. Maestro, P. Reviriego, "Energy Efficiency in Industrial Ethernet: the Case of Powerlink", IEEE Transactions on Industrial Electronics (ISSN: 0278-0046), Vol. 57, No 8, August 2010, pp. 2896-2903.
P. Reviriego, J.A. Hernández, D. Larrabeiti, J.A. Maestro, "Burst Transmission in Energy Efficient Ethernet", IEEE Internet Computing (ISSN: 1089-7801), Vol. 14, No 4, July/August 2010, pp. 50-57.
P. Reviriego, J.A. Maestro, S. Baeg, "Optimizing Scrubbing Sequences for Advanced Computer Memories", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 2, No 2, June 2010, pp. 192-200.
P. Reviriego, J.A. Maestro, C. Bleakley, "Reliability Analysis of Memories Protected with BICS and a per-Word Parity Bit", ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 15, No 2, February 2010, pp. 18:1-18:15.
P. Reviriego, J.A. Hernández, D. Larrabeiti, J.A. Maestro, "Performance Evaluation of Energy Efficient Ethernet", IEEE Communications Letters (ISSN: 1089-7798), Vol. 13, No 9, September 2009, pp. 697-699.
J.A. Maestro, P. Reviriego, "Selection of the Optimal Memory Configuration in a System Affected by Soft Errors", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 9, No 3, September 2009, pp. 403-411.
O. Ruano, J.A. Maestro, P. Reviriego, "A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 56, No 4, August 2009, pp. 2091-2102.
J.A. Maestro, P. Reviriego, "Reliability of Single-Error Correction Protected Memories", IEEE Transactions on Reliability (ISSN: 0018-9529), Vol. 58, No 1, March 2009, pp. 193-201.
P. Reviriego, J.A. Maestro, "Study of the Effects of Multibit Error Correction Codes on the Reliability of Memories in the Presence of MBUs", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 9, No 1, March 2009, pp. 31-39.
P. Reviriego, J.A. Maestro, "Efficient Error Detection Codes for Multiple Bit Upset Correction in SRAMs with BICS", ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 14, No 1, January 2009, pp. 18:1-18:10.
P. Reviriego, J.A. Maestro, O. Ruano, "Efficient Protection Techniques Against SEUs for Adaptive Filters: An Echo Canceller Case Study", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 55, No 3, June 2008, pp. 1700-1707.
P. Reviriego, J.A. Maestro, C. Cervantes, "Reliability Analysis of Memories Suffering Multiple Bit Upsets", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 7, No 4, December 2007, pp. 592-601.
P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "New Protection Techniques against SEUs for Moving Average Filters in a Radiation Environment", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 54, No 4, August 2007, pp. 957-964.

Other Journals Indexed in JCR

J.L. García-Dorado, E. Magaña, P. Reviriego, M. Izal, D. Morató, J.A. Maestro, J. Aracil, "Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network", The Journal of Supercomputing (ISSN: 0920-8542), 2012 (in press).
P. Reviriego, C. Bleakley, J.A. Maestro, "Signal Shaping Dual Modular Redundancy for Soft Error Tolerant Finite Impulse Response Filters", IET Electronic Letters (ISSN: 0013-5194), Vol. 47, No 23, November 2011, pp. 1272-1273.
O. Ruano, J.A. Maestro, P. Reviriego, "A Fast and Efficient Technique to Apply Selective TMR through Optimization", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 12, December 2011, pp. 2388-2401.
D. Larrabeiti, P. Reviriego, J.A. Hernández, J.A. Maestro, M. Urueña, "Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability", Optical Switching and Networking (ISSN: 1573-4277), Vol. 8, No 3, July 2011, pp. 131-138.
C. Bleakley, P. Reviriego, J.A. Maestro, "Low-Complexity Concurrent Error Detection for Convolution with Fast Fourier Transforms", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 6, June 2011, pp. 1152-1156.
J.A. Maestro, P. Reviriego, C. Argyrides, D.K. Pradhan, "Fault Tolerant Single Error Correction Encoders", Journal of Electronic Testing: Theory and Applications (ISSN: 0923-8174), Vol. 27, No 2, April 2011, pp. 215-218.
P. Reviriego, S. Liu, J.A. Maestro, "Mitigation of Permanent Faults in Adaptive Equalizers", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 3, March 2011, pp. 703-710.
P. Reviriego, C. Bleakley, J.A. Maestro, "Very-Low-Complexity Concurrent Error Detection for Transform-based Filters", IET Electronic Letters (ISSN: 0013-5194), Vol. 46 , No 25, December 2010 , pp. 1677-1679.
J.A. Maestro, P. Reviriego, "A Method to Eliminate the Event Accumulation Problem from a Memory Affected by Multiple Bit Upsets", Microelectronics Reliability (ISSN: 0026-2714), Vol. 49, No 7, July 2009, pp. 707-715.
J.A. Maestro, P. Reviriego, P. Reyes, O. Ruano, "Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study", Integration, the VLSI Journal (ISSN: 0167-9260), Vol. 42, No 2, January 2009, pp. 128-136.
P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study", Journal of VLSI Signal Processing Systems for Signal Image and Video Technology (ISSN: 0922-5773), Vol. 52, No 3, September 2008, pp. 231-247.

Highlighted Conferences

P. Reviriego, J.A. Maestro, S. Baeg, "Designing Ad-hoc Scrubbing Sequences to Improve Memory Reliability against Soft Errors", Proc. of the Design Automation Conference (DAC'11), San Diego (USA), June 2011, pp. 700-705.
J.A. Maestro, P. Reviriego, "Study of the Effects of MBUs on the Reliability of a 150 nm SRAM Device", Proc. of the Design Automation Conference (DAC'08), Anaheim (USA), June 2008, pp. 930-935.

Other International Conferences

P. Reviriego, M. Flanagan, J.A. Maestro, "Efficient Multibit Error Correction for Memory Applications Using Euclidean Geometry Codes", Proc. of the RADECS 2011 conference, Sevilla (Spain), September 2011 (in press).
P. Reviriego, J.A. Maestro, I. López, J.A. de Agapito, "Soft Error Tolerant Infinite Impulse Response Filters Using Reduced Precision Replicas", Proc. of the RADECS 2011 conference, Sevilla (Spain), September 2011 (in press).
P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance", Proc. of the IFIP/TC6 NETWORKING 2011 Workshop on Sustainable Networking (SUNSET), Valencia (Spain), May 2011 (in press).
P. Reviriego, K. Christensen, A. Sánchez-Macián, J.A. Maestro, "Using Coordinated Transmission with Energy Efficient Ethernet", Proc. of the IFIP/TC6 NETWORKING 2011 Conference, Valencia (Spain), May 2011, pp. 160-171. [Download NS2 simulation codes here]
O. Ruano, J.A. Maestro, P. Reviriego, "Validation and Optimization of TMR Protections for Circuits in Radiation Environments", Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS'11), Cottbus (Germany), April 13-15, 2011, pp. 399-400.
S.Y. Lee, S. Baeg, P. Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors", Proc. of the IEEE International Integrated Reliability Workshop (IIRW'10), Stanford (USA), October 2010, pp.114-117.
S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J.A. Maestro, M. Alderighi, "A Fault Tolerant Adaptive Equalizer implemented with Reconfigurable SRAM-based FPGAs", Proc. of the RADECS 2010 conference, Längenfeld (Austria), September 2010 (in press).
P. Reviriego, C. Argyrides, J.A. Maestro, D.K. Pradhan, "Enabling Performance versus Reliability Tradeoffs in Memories Using Block Parity", Proc. of the RADECS 2010 conference, Längenfeld (Austria), September 2010 (in press).
P. Reviriego, D. Larrabeiti, J.A. Maestro, "Would Energy Efficient Ethernet be effective on 10Gbps Optical Links?", Proc. of the Optical Society of America (OSA) Photonics in Switching meeting, Monterey (USA), July 2010 (in press).
P. Reviriego, A. Sánchez-Macián, J.A. Maestro, C. Bleakley, "Increasing the MTU size for Energy Efficiency in Ethernet", Proc. of the 21st IET Irish Signals and Systems Conference (ISSC'10), Cork (Ireland), 23rd - 24th June 2010.
P. Reviriego, D. Larrabeiti, J.A. Maestro, J.A. Hernández, P. Afshar, L. G. Kazovsky, "Energy Efficiency in 10Gbps Ethernet Transceivers: Copper versus Fiber", Proc. of the Optical Fiber Communication Conference and Exposition (OFC/NFOEC'10), San Diego (USA), March 2010 (in press).
P. Reviriego, J.A. Maestro, S. Baeg, S. Weng, R. Wong, "Selection of the Optimal Interleaving Distance for Memories Suffering MCUs", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 499-502.
S. Liu, P. Reviriego, J.A. Maestro, "Fault Tolerant FIR Filters Using Hamming Codes", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 484-487.
C. Argyrides, P. Reviriego, D.K. Pradhan, J.A. Maestro, "A Novel Error Correction Technique for Adjacent Errors", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 480-483.
P. Reviriego, J.A. Maestro, A. O'Donnell, C. Bleakley, "Soft Error Detection and Correction for FFT Based Convolution using Different Block Lengths", Proc. of IEEE International On-Line Testing Symposium (IOLTS'09), Lisbon (Portugal), June 2009, pp. 138-143.
A. O'Donnell, C. Bleakley, P. Reviriego, J.A. Maestro, "Efficient Concurrent Error Detection and Correction of Soft Errors in NTT-based Convolutions", Proc. of the 20th IET Irish Signals and Systems Conference (ISSC'09), Dublin (Ireland), June 2009.
S. Baeg, P. Reviriego, J.A. Maestro, S. Wen, R. Wong, "Analysis of a Multiple Cell Upset Failure Model for Memories", Proc. of the 2009 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'09), Stanford University (USA), March 2009, http://www.selse.org/program.html .
P. Reviriego, J.A. Maestro, "A Technique to Calculate the MBU Distribution of a Memory under Radiation Suffering the Event Accumulation Problem", Proc. of the RADECS 2008 conference, Jyväskylä (Finland), September 2008, pp. 393-396.
O. Ruano, P. Reviriego, J.A. Maestro, "Automatic Insertion of Selective TMR for SEU Mitigation", Proc. of the RADECS 2008 conference, Jyväskylä (Finland), September 2008, pp. 284-287.
O. Ruano, J.A. Maestro, P. Reviriego, "Performance Analysis and Improvements for a Simulation-based Fault Injection Platform", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'08), Cambridge (U.K.), June 2008, pp. 2299-2304.
O. Ruano, P. Reviriego, J.A. Maestro, "A New EDAC Technique against Soft Errors based on Pulse Detectors", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'08), Cambridge (U.K.), June 2008, pp. 2293-2298.
P. Reviriego, P. Reyes, J.A. Maestro, O. Ruano, "System Knowledge-Based Techniques against SEUs for Adaptive Filters", Proc. of the RADECS 2007 conference, Deauville (France), September 2007, pp. 48-52.
O. Ruano, P. Reyes, J.A. Maestro, L. Sterpone, P. Reviriego, "An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques", Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), Kraków (Poland), April 2007, pp. 261-266.
O. Ruano, J.A. Maestro, P. Reyes, P. Reviriego, "A Simulation Platform for the Study of Soft Errors on Signal Processing Circuits through Software Fault Injection", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo (Spain), June 2007, pp. 3316-3321.
P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "A New Protection Technique for Finite Impulse Response (FIR) Filters in the Presence of Soft Errors", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo (Spain), June 2007, pp. 3328-3333.
P. Reyes, P. Reviriego, O. Ruano, J.A. Maestro, "Efficient Structures for the Implementation of Moving Average Filters in the Presence of SEUs using System Knowledge", Proc. of the RADECS 2006 conference, Athens (Greece), September 2006, pp. 102-105.

Other Publications

P. Reviriego, J.A. Maestro, "Optimize Energy Efficient Ethernet (IEEE 802.3az) performance in bundled links", EE Times, August 2011, http://www.eetimes.com/design/industrial-control/4218670/Optimize-Energy-Efficient-Ethernet--IEEE-802-3az--performance-in-bundled-links?Ecosystem=communications-design .
P. Reviriego, L. Holst, J.A. Maestro, "On the Expected Longest Length Probe Sequence for Hashing with Separate Chaining", Journal of Discrete Algorithms (ISSN 1570-8667), Vol. 9, No 3, September 2011, pp. 307-312.
D. Larrabeiti, P. Reviriego, J. Hernández, J.A. Maestro, M. Urueña, "Towards an Energy Efficient 10Gb/s Optical Ethernet: performance analysis and viability", Optical Switching and Networking (ISSN: 1573-4277), Vol. 8, No 3, July 2011, pp. 131-138.
P. Reviriego, J.A. Maestro, C.J. Bleakley, "Implications of Energy Efficient Ethernet for Hubs and Switches", International Journal of Communications Networks and Distributed Systems (ISSN 1754-3916), Vol. 6, No. 1, January 2011, pp. 3-11.
P. Reviriego, J.A. Maestro, P. Congdon, "Reduce latency in energy efficient Ethernet switches with early destination lookup”, CommsDesign, April 2010, http://www.commsdesign.com/design_corner/showArticle.jhtml;?articleID=224400657 .
P. López, M. Cid , P. Reviriego, J.A. Maestro, D. Larrabeiti, "Ahorro Energético en Redes Ethernet mediante Adaptación Automática de Velocidad", Proc. of Telecom I+D 2009, Madrid, November 2009.
P. Reviriego, C. Bleakley, J.A. Maestro, "Energy efficiency in Ethernet receivers", CommsDesign, September 2009, http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=220000945 .
O. Ruano, J.A. Maestro, P. Reyes, P. Reviriego, "Plataforma de Simulación y Análisis para el Estudio de los Efectos de la Radiación sobre Circuitos de Comunicaciones", Proc. of Telecom I+D 2006, Madrid, November 2006.

© 2006-2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, collecting new collected works for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.






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