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The following papers have been produced based on our research work:

Book Chapters

  • S. Pontarelli, J.A. Maestro, P. Reviriego, "Dependability Solutions", in "Dependable Multicore Architectures at Nanoscale" (ISBN: 978-3319544212), Springer, Ed. M. Ottavi, D. Gizopoulos, S. Pontarelli, October 2017, pp. 155-188.
  • V. Izosimov, A. Paschalis, P. Reviriego, H. Manhaeve, "Application Specific Solutions", in "Dependable Multicore Architectures at Nanoscale" (ISBN: 978-3319544212), Springer, Ed. M. Ottavi, D. Gizopoulos, S. Pontarelli, October 2017, pp. 189-216.
  • P. Reviriego, K. Christensen, M. Bennett, B. Nordman, J.A. Maestro, "Energy Efficiency in Ethernet", in "Green Communications: Principles, Concepts and Practice" (ISBN: 978-1-1187-5926-4), Wiley, Ed. K. Samdanis, P. Rost, A. Maeder, M. Meo, C. Verikoukis, September 2015, pp. 277-290.
  • J.A. Maestro, P. Reviriego, M. Flanagan, "Error Correction Coding for Electronic Circuits", in "Energy-Efficient Fault-Tolerant Systems" (ISBN: 978-1-4614-4192-2), Springer, Ed. J. Mathew, R.A. Shafik, D.K. Pradhan, 2014, pp. 137-168.
  • P. Reviriego, J.A. Maestro, "Soft Errors in Digital Circuits: Overview and Protection Techniques for Digital Filters", in "Radiation Effects in Semiconductors" (ISBN: 978-1-4398-2694-2), CRC Press, Ed. Kris Iniewski, August 2010, pp. 357-384.

Journals indexed in JCR
See copyright note at the end of this page

  1. A. Sánchez-Macián, L. Aranda, P. Reviriego, V. Kiani, J.A. Maestro, "Enhancing Instruction TLB Resilience to Soft Errors", IEEE Transactions on Computers (ISSN: 0018-9340), 2018 (in press).
  2. L. Aranda, P. Reviriego, R. González-Toral, J.A. Maestro, "Protection Scheme for Star Tracker Images", IEEE Transactions on Aerospace and Electronic Systems (ISSN: 0018-9251), 2018 (in press).
  3. A. Ullah, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 4, December 2018, pp. 636-638.
  4. A. Cóbreces, A. Regadío, J. Tabero, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "SEU and SEFI Error Detection and Correction on a DDR3 Memory System", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 91, December 2018, pp. 23-30.
  5. L. Aranda, P. Reviriego, J.A. Maestro, "Protecting Image Processing Pipelines Against Configuration Memory Errors in SRAM-based FPGAs", Electronics, MDPI (ISSN: 2079-9292), Vol. 7, No 11, November 2018, pp. 1-10.
  6. R. González-Toral, P. Reviriego, J.A. Maestro, Z. Gao, "A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-based FPGAs", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 65, No 7, July 2018, pp. 1039-1045.
  7. R. González-Toral, P. Reviriego, J.A. Maestro, C. Argyrides, "A Fast Technique to Reduce Power Consumption on Linear Block Codes Used to Protect Registers", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 2, June 2018, pp. 189-196.
  8. A. Ullah, P. Reviriego, J.A. Maestro, "An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 65, No 4, April 2018, pp. 989-996.
  9. J. Tabero, A. Regadío, C. Pérez, J. Pazos, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "Modular Fault Tolerant Processor Architecture on a SoC for Space", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 83, April 2018, pp. 84-90.
  10. R. González-Toral, S. Liu, P. Reviriego, J.A. Maestro, "Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 65, No 4, April 2018, pp. 1293-1302.
  11. J. Martínez, J.A. Maestro, P. Reviriego, "Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 1, March 2018, pp. 70-79.
  12. S. Liu, J. Li, P. Reviriego, M. Ottavi, "A Double Error Correction Code for 32-bit Data Words with Efficient Decoding", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 1, March 2018, pp. 125-127.
  13. A. Ullah, P. Reviriego, S. Pontarelli, J.A. Maestro, "Majority Voting-based Reduced Precision Redundancy Adders", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 1, March 2018, pp. 122-124.
  14. L. Aranda, P. Reviriego, J.A. Maestro, "A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response (FIR) Filters Implemented in SRAM-based FPGAs through Fault Injection", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 65, No 3, March 2018, pp. 376-380.
  15. Z. Gao, M. Zhou, P. Reviriego, J.A. Maestro, "Efficient Fault Tolerant Design for Parallel Matched Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 65, No 3, March 2018, pp. 366-370.
  16. S. Liu, P. Reviriego, J.A. Maestro, L. Xiao, "Fault Tolerant Encoders for Single Error Correction and Double Adjacent Error Correction Codes", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 81, February 2018, pp. 167-173.
  17. J. Li, P. Reviriego, L. Xiao, C. Argyrides, J. Li, "Extending 3-bit Burst Error Correction Codes with Quadruple Adjacent Error Correction", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 26, No 2, February 2018, pp. 221-229.
  18. A. Ramos, A. Ullah, P. Reviriego, J.A. Maestro, "Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 67, No 2, February 2018, pp. 299-304.
  19. Z. Gao, Q. Jing, Y. Li, P. Reviriego, J.A. Maestro, "An Efficient Fault Tolerance Design for Integer Parallel Matrix-Vector Multiplications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 26, No 1, January 2018, pp. 211-215.
  20. J. Martínez, J.A. Maestro, P. Reviriego, "A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture", IEEE Computer Architecture Letters (ISSN: 1556-6056), Vol. 16, No 2, July-December 2017, pp. 103-106.
  21. A. Sánchez-Macián, P. Reviriego, J. Tabero, A. Regadío, J.A. Maestro, "SEFI Protection for Nanosat 16-bit Chip On-Board Computer Memories", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 17, No 4, December 2017, pp. 698-707.
  22. S. Liu, P. Reviriego, L. Xiao, "Evaluating Direct Compare for Double Error Correction Codes", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 17, No 4, December 2017, pp. 802-804.
  23. A. Ramos, J.A. Maestro, P. Reviriego, "Characterizing a RISC-V SRAM-based FPGA Implementation against Single Event Upsets Using Fault Injection", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 78, November 2017, pp. 205-211.
  24. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, S. Liu, "Single Event Transient Tolerant Bloom Filter Implementations", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 66, No 10, October 2017, pp. 1831-1836.
  25. L. Aranda, P. Reviriego, J.A. Maestro, "Error Detection Technique for a Median Filter", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 64, No 8, August 2017, pp. 2219-2226.
  26. P. Reviriego, S. Liu, A. Sánchez-Macián, L. Xiao, J.A. Maestro, "A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes", IEEE Transactions on Reliability (ISSN: 0018-9529), Vol. 66, No 2, June 2017, pp. 518-528.
  27. S. Liu, P. Reviriego, L. Xiao, J.A. Maestro, "A Method to Recover Critical Bits under a Double Error in SEC-DED Protected Memories", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 73, June 2017, pp. 92-96.
  28. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Combined Modular Key and Data Error Protection for Content-Addressable Memories", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 66, No 6, June 2017, pp. 1085-1090.
  29. P. Reviriego, S. Pontarelli, J.A. Maestro, "A Method to Protect Cuckoo Filters from Soft Errors", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 72, May 2017, pp. 85-89.
  30. S. Liu, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, L. Xiao, "Comments on 'Extend orthogonal Latin square codes for 32-bit data protection in memory applications' Microelectron. Reliab. 63, 278–283 (2016)", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 69, February 2017, pp. 126-129.
  31. P. Reviriego, J. López, M. Sánchez-Renedo, V. Petrovic, J.F. Dufour, J.S. Weil, "The Space Ethernet PHYsical Layer Transceiver (SEPHY) Project: A Step Towards Reliable Ethernet in Space", IEEE Aerospace and Electronic Systems Magazine (ISSN: 0885-8985), Vol. 32, No 1, January 2017, pp. 24-28.
  32. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Optimizing the Implementation of SEC-DAEC Codes in FPGAs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 24, No 12, December 2016, pp. 3538-3542.
  33. P. Reviriego, S. Liu, L.Y. Xiao, J.A. Maestro, "Efficient Implementation of Single Event Upset Tolerant Register Comparison", IET Electronic Letters (ISSN: 0013-5194), Vol. 52, No 23, November 2016, pp. 1922-1923.
  34. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 63, No 11, November 2016, pp. 1933-1943.
  35. M. Demirci, P. Reviriego, J.A. Maestro, "Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 65, No 9, September 2016, pp. 2932-2938.
  36. P. Reviriego, M. Demirci, J. Tabero, A. Regadío, J.A. Maestro, "DMR+: An efficient alternative to TMR to protect registers in Xilinx FPGAs", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 63, August 2016, pp. 314-318.
  37. M. Mitzenmacher, P. Reviriego, S. Pontarelli, "OMASS: One Memory Access Set Separation", IEEE Transactions on Knowledge and Data Engineering (ISSN: 1041-4347), Vol. 28, No 7, July 2016, pp. 1940-1943.
  38. S. Liu, P. Reviriego, L. Xiao, J.A. Maestro, "Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 16, No 2, June 2016, pp. 269-271.
  39. P. Reviriego, S. Liu, A. Sánchez-Macián, L.Y. Xiao, J.A. Maestro, "Unequal Error Protection Codes Derived from SEC-DED codes", IET Electronic Letters (ISSN: 0013-5194), Vol. 52, No 8, April 2016, pp. 619-620.
  40. P. Reviriego, S. Liu, L. Xiao, J.A. Maestro, "An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 24, No 4, April 2016, pp. 1603-1606.
  41. S. Pontarelli, P. Reviriego, J.A. Maestro, "Improving Counting Bloom Filter Performance with Fingerprints", Information Processing Letters, Elsevier (ISSN: 0020-0190), Vol. 116, No 4, April 2016, pp. 304–309.
  42. P. Reviriego, M. Demirci, A. Evans, J.A. Maestro, "A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 63, No 2, February 2016, pp. 171-175.
  43. Z. Gao, P. Reviriego, Z. Xu, X. Su, M. Zhao, J. Wang, J.A. Maestro, "Fault Tolerant Parallel FFTs using Error Correction Codes and Parseval Checks", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 24, No 2, February 2016, pp. 769-773.
  44. S. Liu, P. Reviriego, A. Sánchez-Macián, L.Y. Xiao, J.A. Maestro, "Odd-weight-column SEC-DED-TAED codes", IET Electronic Letters (ISSN: 0013-5194), Vol. 52, No 2, January 2016, pp. 119-120.
  45. S. Pontarelli, P. Reviriego, J.A. Maestro, "Parallel d-Pipeline: a Cuckoo Hashing Implementation for Increased Throughput", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 65, No 1, January 2016, pp. 326-331.
  46. P. Reviriego, K. Christensen, J.A. Maestro, "A Comment on 'Fast Bloom Filters and Their Generalization'", IEEE Transactions on Parallel and Distributed Systems (ISSN: 1045-9219), Vol. 27, No 1, January 2016, pp. 303-304.
  47. M. Demirci, P. Reviriego, J.A. Maestro, "Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 56, No 1, January 2016, pp. 221-227.
  48. L.J. Saiz-Adalid, P. Reviriego, P. Gil, S. Pontarelli, J.A. Maestro, "MCU Tolerance in SRAMs through Low Redundancy Triple Adjacent Error Correction", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 23, No 10, October 2015, pp. 2332-2336.
  49. Z. Gao, P. Reviriego, Z. Xu, X. Su, J. Wang, J.A. Maestro, "Efficient Coding Schemes for Fault Tolerant Parallel Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 62, No 7, July 2015, pp. 666-670.
  50. S. Pontarelli, P. Reviriego, M. Ottavi, J.A. Maestro, "Low Delay Single Symbol Error Correction Codes based on Reed Solomon Codes", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 64, No 5, May 2015, pp. 1497-1501.
  51. P. Reviriego, S. Pontarelli, A. Evans, J.A. Maestro, "A Class of SEC-DED-DAEC codes derived from Orthogonal Latin Square Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 23, No 5, May 2015, pp. 968-972.
  52. G. Rodríguez, P. Reviriego, J.A. Hernández, "Packet Coalescing Strategies for Energy Efficient High-Speed Communications over Plastic Optical Fibres", Journal of Optical Communications and Networking (ISSN: 1943-0620), Vol. 7, No 4, April 2015, pp. 253-263.
  53. M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M.K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego et al., "Dependable Multicore Architectures at Nanoscale: The View From Europe", IEEE Design & Test of Computers (ISSN: 0740-7475), Vol. 32, No 2, March-April 2015, pp. 17-28.
  54. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "A Synergetic Use of Bloom Filters for Error Detection and Correction", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 23, No 3, March 2015, pp. 584-587.
  55. Z. Gao, P. Reviriego, W. Pan, Z. Xu, M. Zhao, J. Wang, J.A. Maestro, "Fault Tolerant Parallel Filters based on Error Correction Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 23, No 2, February 2015, pp. 384-387.
  56. P. Reviriego, J.A. Maestro, "Efficient Error Detection in Multiple Way Tables", IET Electronic Letters (ISSN: 0013-5194), Vol. 51, No 1, January 2015, pp. 50-52.
  57. M. Demirci, P. Reviriego, J.A. Maestro, "Optimized Parallel Decoding of Difference Set Codes for High Speed Memories", Microelectronics Reliability (ISSN: 0026-2714), Vol. 54, No 11, November 2014, pp. 2645–2648.
  58. P. Reviriego, J.A. Maestro, "Implementing Error Detection in Fast Counting Bloom Filters", IET Electronic Letters (ISSN: 0013-5194), Vol. 50, No 22, October 2014, pp. 1602-1604.
  59. S. Pontarelli, P. Reviriego, J.A. Maestro, "Efficient Flow Sampling with Back-annotated Cuckoo Hashing", IEEE Communications Letters (ISSN: 1089-7798), Vol. 18, No 10, October 2014, pp. 1695-1698.
  60. P. Reviriego, J. Martínez, S. Pontarelli, J.A. Maestro, "A Method to Design SEC-DED-DAEC codes with Optimized Decoding", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 14, No 3, September 2014, pp. 884-889.
  61. P. Reviriego, S. Pontarelli, M. Ottavi, J.A. Maestro, "FastTag: A Technique to Protect Cache Tags against Soft Errors", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 14, No 3, September 2014, pp. 935-937.
  62. V. Sivaraman, P. Reviriego, Z. Zhao, A. Sánchez-Macián, A. Vishwanath, J.A. Maestro, C. Russell, "An Experimental Power Profile of Energy Efficient Ethernet Switches", Computer Communications, Elsevier (ISSN: 0140-3664), Vol. 50, September 2014, pp. 110–118.
  63. P. Reviriego, S. Can, C. Eryilmaz, J. Maestro, O. Ergin, "Exploiting Processor Features to Implement Error Detection in Reduced Precision Matrix Multiplications", Microprocessors and Microsystems, Elsevier (ISSN: 0141-9331), Vol. 38, No 6, August 2014, pp. 581-584.
  64. P. Reviriego, S. Pontarelli, A. Sánchez-Macián, J.A. Maestro, "A Method to Extend Orthogonal Latin Square Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 22, No 7, July 2014, pp. 1635-1639.
  65. P. Reviriego, S. Pontarelli, J.A. Maestro, "Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing", IEEE Communications Letters (ISSN: 1089-7798), Vol. 18, No 5, May 2014, pp. 885–888.
  66. S. Pontarelli, P. Reviriego, M. Mitzenmacher, "Improving the performance of Invertible Bloom Lookup Tables", Information Processing Letters, Elsevier (ISSN: 0020-0190), Vol. 114, No 4, April 2014, pp. 185–191.
  67. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes through Selective Shortening and Bit Placement", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 14, No 1, March 2014, pp. 574–576.
  68. Z. Gao, P. Reviriego, X. Li, J.A. Maestro, M. Zhao, J. Wang, "A Fault Tolerant Implementation of the Goertzel Algorithm", Microelectronics Reliability (ISSN: 0026-2714), Vol. 54, No 1, January 2014, pp. 335–337.
  69. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "Efficient Implementation of Error Correction Codes in Hash Tables", Microelectronics Reliability (ISSN: 0026-2714), Vol. 54, No 1, January 2014, pp. 338–340.
  70. P. Reviriego, S. Pontarelli, J.A. Maestro, "Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 21, No 12, December 2013, pp. 2334-2338.
  71. P. Reviriego, S. Pontarelli, J.A. Maestro, "Optimised Decoding of Odd-Weight Single Error Correction Double Error Detection Codes with 64 Bits", IET Electronic Letters (ISSN: 0013-5194), Vol. 49, No 25, December 2013, pp. 1617-1618.
  72. J.A. Maestro, P. Reviriego, S. Baeg, S. Wen, R. Wong, "Soft Error Tolerant Content Addressable Memories (CAMs) Using Error Detection Codes and Duplication", Microprocessors and Microsystems, Elsevier (ISSN: 0141-9331), Vol. 37, No 8, November 2013, pp. 1103-1107.
  73. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "Reducing the Cost of Single Error Correction With Parity Sharing", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 13 , No 3, September 2013, pp. 420-422.
  74. S. Pontarelli, P. Reviriego, J.A. Maestro, C. Bleakley, "Low Complexity Concurrent Error Detection for Complex Multiplication", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 62, No 9, September 2013, pp. 1899-1903.
  75. P. Reviriego, O. Ruano, M. Flanagan, S. Pontarelli, J.A. Maestro, "An Efficient Technique to Protect Serial Shift Registers against Soft Errors", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 60, No 8, August 2013, pp. 512-516.
  76. Z. Gao, P. Reviriego, W. Pan, Z. Xu, M. Zhao, J. Wang, J.A. Maestro, "Efficient Arithmetic Residue Based SEU-tolerant FIR Filter Design", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 60, No 8, August 2013, pp. 497-501.
  77. P. Reviriego, R. Pérez de Aranda, C. Pardo, "Introducing Energy Efficiency in the VDE 0885-763-1 Standard for High Speed Communication over Plastic Optical Fibers", IEEE Communications Magazine (ISSN: 0163-6804), Vol. 51, No 8, August 2013, pp. 97-102.
  78. Z. Gao, P. Reviriego, M. Zhao, J. Wang, J.A. Maestro, "Efficient Single Event Upset-Tolerant FIR Filter Design Based on Residue Number for OBP Satellite Communication Systems", China Communications (ISSN: 1673-5447), Vol. 10, No 8, August 2013, pp. 55-67.
  79. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 60, No 7, July 2013, pp. 432-436.
  80. P. Reviriego, C. Bleakley, J.A. Maestro, "Diverse Double Modular Redundancy: A New Direction for Soft Error Detection and Correction", IEEE Design & Test of Computers (ISSN: 0740-7475), Vol. 30, No 2, March-April 2013, pp. 87-95.
  81. C. Argyrides, P. Reviriego, J.A. Maestro, "Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors", IEEE Transactions on Reliability (ISSN: 0018-9529), Vol. 62, No 1, March 2013, pp. 238-243.
  82. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "A Method to Construct Low Delay Single Error Correction (SEC) Codes for Protecting Data Bits Only", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ISSN: 0278-0070), Vol. 32, No 3, March 2013, pp. 479-483. [The Verilog source code for the SEC and SEC-DED codes proposed in this paper is available here]
  83. A. Oliva, T.R. Vargas, J.C. Guerri, J.A. Hernandez, P. Reviriego, "Performance analysis of Energy Efficient Ethernet on Video Streaming Servers", Computer Networks, Elsevier (ISSN: 1389-1286), Vol. 57, No 3, February 2013, pp. 599-608.
  84. I.B. Karsli, P. Reviriego, M.F. Balli, O. Ergin, J.A. Maestro, "Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values", IEEE Computer Architecture Letters (ISSN: 1556-6056), Vol. 12, No 1, January-June 2013, pp. 13-16.
  85. P. Reviriego, J.A. Maestro, M. Flanagan, "Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 21, No 1, January 2013, pp. 156-159.
  86. J.L. García-Dorado, E. Magaña, P. Reviriego, M. Izal, D. Morató, J.A. Maestro, J. Aracil, "Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network", The Journal of Supercomputing, Springer (ISSN: 0920-8542), Vol. 62, No 3, December 2012, pp. 1284-1304.
  87. P. Reviriego, M. Flanagan, S. Liu, J.A. Maestro, "Multiple Cell Upset Correction in Memories Using Difference Set Codes", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 59, No 11, November 2012, pp. 2592-2599.
  88. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "Low-Cost Single Error Correction Multiple Adjacent Error Correction Codes", IET Electronics Letters (ISSN: 0013-5194), Vol. 48, No 23, November 2012, pp. 1470-1472.
  89. P. Reviriego, O. Ruano, J.A. Maestro, "Implementing concurrent Error Detection in Infinite-Impulse-Response Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 59, No 9, September 2012, pp. 583-586.
  90. P. Reviriego, S. Pontarelli, C. Bleakley, J.A. Maestro, "Area Efficient Concurrent Error Detection and Correction for Parallel Filters", IET Electronic Letters (ISSN: 0013-5194), Vol. 48, No 20, September 2012, pp. 1258-1260.
  91. P. Reviriego, M. Flanagan, S. Liu, J.A. Maestro, "On the Use of Euclidean Geometry Codes for Efficient Multibit Error Correction on Memory Systems", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 59, No 4, August 2012, pp. 824-828.
  92. P. Reviriego, C. Argyrides, J.A. Maestro, "Efficient Error Detection in Double Error Correction BCH Codes for Memory Applications", Microelectronics Reliability (ISSN: 0026-2714), Vol. 52, No 7, July 2012, pp. 1528–1530.
  93. S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J.A. Maestro, M. Alderighi, H. Mecha, "Comparison of the Susceptibility to Soft Errors of SRAM-based FPGA Error Correction Codes Implementations", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 59, No 3, June 2012, pp. 619-624.
  94. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes through Selective Bit Placement", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 12, No 2, June 2012, pp. 357-362.
  95. P. Reviriego, M. Flanagan, S. Liu, J.A. Maestro, "Error-Detection Enhanced Decoding of Difference Set Codes for Memory Applications", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 12, No 2, June 2012, pp. 335-340.
  96. P. Reviriego, J.A. Maestro, J.A. Hernández, D. Larrabeiti, "Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate", Transactions on Emerging Telecommunications Technologies (formerly known as European Transactions on Telecommunications) (ISSN: 1124-318X), Vol. 23, No 3, April 2012, pp. 227-233.
  97. P. Reviriego, M. Flanagan, J.A. Maestro, "A (64,45) Triple Error Correction Code for Memory Applications", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 12, No 1, March 2012, pp. 101-106.
  98. S. Liu, P. Reviriego, J.A. Maestro, "Efficient Majority Logic Fault Detection with Difference-Set Codes for Memory Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 20, No 1, January 2012, pp. 148-156.
  99. O. Ruano, J.A. Maestro, P. Reviriego, "A Fast and Efficient Technique to Apply Selective TMR through Optimization", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 12, December 2011, pp. 2388-2401.
  100. P. Reviriego, C. Bleakley, J.A. Maestro, "Signal Shaping Dual Modular Redundancy for Soft Error Tolerant Finite Impulse Response Filters", IET Electronic Letters (ISSN: 0013-5194), Vol. 47, No 23, November 2011, pp. 1272-1273.
  101. J.A. Maestro, P. Reviriego, S. Baeg, S. Wen, R. Wong, "Mitigating the Effects of Large Multiple Cell Upsets (MCUs) in Memories”, ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 16, No 4, October 2011, pp. 45:1-45:10.
  102. P. Reviriego, C. Bleakley, J.A. Maestro, A. O’Donnell, "Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform Based Convolution", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 60, No 10, October 2011, pp. 1511-1516.
  103. P. Reviriego, C. Bleakley, J.A. Maestro, "Structural DMR: a Technique for Implementation of Soft Error Tolerant FIR Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 58, No 8, August 2011, pp. 512-516.
  104. D. Larrabeiti, P. Reviriego, J.A. Hernández, J.A. Maestro, M. Urueña, "Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability", Optical Switching and Networking (ISSN: 1573-4277), Vol. 8, No 3, July 2011, pp. 131-138.
  105. C. Bleakley, P. Reviriego, J.A. Maestro, "Low-Complexity Concurrent Error Detection for Convolution with Fast Fourier Transforms", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 6, June 2011, pp. 1152-1156.
  106. S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J.A. Maestro, M. Alderighi, "Increasing Reliability of FPGA-based Adaptive Equalizers in the Presence of Single Event Upsets", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 58, No 3, June 2011, pp. 1072-1077.
  107. P. Reviriego, C. Argyrides, J.A. Maestro, D.K. Pradhan, "Improving Memory Reliability against Soft Errors Using Block Parity", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 58, No 3, June 2011, pp. 981-986.
  108. P. Reviriego, K. Christensen, J. Rabanillo, J.A. Maestro, "An Initial Evaluation of Energy Efficient Ethernet", IEEE Communications Letters (ISSN: 1089-7798), Vol. 15, No 5, May 2011, pp. 578-580.
  109. J.A. Maestro, P. Reviriego, C. Argyrides, D.K. Pradhan, "Fault Tolerant Single Error Correction Encoders", Journal of Electronic Testing: Theory and Applications (ISSN: 0923-8174), Vol. 27, No 2, April 2011, pp. 215-218.
  110. P. Reviriego, B. Huiszoon, V. López, R.B. Coenen, J.A. Hernández, J.A. Maestro, "Improving Energy Efficiency in IEEE 802.3ba High-Rate Ethernet Optical Links", IEEE Journal of Selected Topics in Quantum Electronics (ISSN 1077-260X), Vol. 17, No 2, March/April 2011, pp. 419-427.
  111. P. Reviriego, S. Liu, J.A. Maestro, "Mitigation of Permanent Faults in Adaptive Equalizers", Microelectronics Reliability (ISSN: 0026-2714), Vol. 51, No 3, March 2011, pp. 703-710.
  112. P. Reviriego, C. Bleakley, J.A. Maestro, "Very-Low-Complexity Concurrent Error Detection for Transform-based Filters", IET Electronics Letters (ISSN: 0013-5194), Vol. 46 , No 25, December 2010 , pp. 1677-1679.
  113. K. Christensen, P. Reviriego, B. Nordman, M. Bennett, M. Mostowfi, J. A. Maestro, "IEEE 802.3az: The Road to Energy Efficient Ethernet", IEEE Communications Magazine (ISSN: 0163-6804), Vol. 48, No 11, November 2010, pp. 50-56.
  114. P. Reviriego, L. Holst, J.A. Maestro, "Number of Events and Time to Failure Distributions for Error Correction Protected Memories", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 10, No 3, September 2010, pp. 381-389.
  115. P. Reviriego, J.A. Maestro, S. Liu, "Efficient Soft Error-Tolerant Adaptive Equalizers", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 57, No 8, August 2010, pp. 2032-2040.
  116. C. Argyrides, P. Reviriego, D.K. Pradhan, J.A. Maestro, "Matrix-Based Codes for Adjacent Error Correction", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2106-2111.
  117. S. Liu, P. Reviriego, J.A. Maestro, "Enhanced Implementations of Hamming Codes to Protect FIR Filters", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2112-2118.
  118. P. Reviriego, J.A. Maestro, S. Baeg, S. Wen, R. Wong, "Protection of Memories Suffering MCUs through the Selection of the Optimal Interleaving Distance", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 57, No 4(1), August 2010, pp. 2124-2128.
  119. J.A. Maestro, P. Reviriego, "Energy Efficiency in Industrial Ethernet: the Case of Powerlink", IEEE Transactions on Industrial Electronics (ISSN: 0278-0046), Vol. 57, No 8, August 2010, pp. 2896-2903.
  120. P. Reviriego, J.A. Hernández, D. Larrabeiti, J.A. Maestro, "Burst Transmission in Energy Efficient Ethernet", IEEE Internet Computing (ISSN: 1089-7801), Vol. 14, No 4, July/August 2010, pp. 50-57.
  121. P. Reviriego, J.A. Maestro, S. Baeg, "Optimizing Scrubbing Sequences for Advanced Computer Memories", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 2, No 2, June 2010, pp. 192-200.
  122. P. Reviriego, J.A. Maestro, C. Bleakley, "Reliability Analysis of Memories Protected with BICS and a per-Word Parity Bit", ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 15, No 2, February 2010, pp. 18:1-18:15.
  123. P. Reviriego, J.A. Hernández, D. Larrabeiti, J.A. Maestro, "Performance Evaluation of Energy Efficient Ethernet", IEEE Communications Letters (ISSN: 1089-7798), Vol. 13, No 9, September 2009, pp. 697-699.
  124. J.A. Maestro, P. Reviriego, "Selection of the Optimal Memory Configuration in a System Affected by Soft Errors", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 9, No 3, September 2009, pp. 403-411.
  125. O. Ruano, J.A. Maestro, P. Reviriego, "A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 56, No 4, August 2009, pp. 2091-2102.
  126. J.A. Maestro, P. Reviriego, "A Method to Eliminate the Event Accumulation Problem from a Memory Affected by Multiple Bit Upsets", Microelectronics Reliability (ISSN: 0026-2714), Vol. 49, No 7, July 2009, pp. 707-715.
  127. J.A. Maestro, P. Reviriego, "Reliability of Single-Error Correction Protected Memories", IEEE Transactions on Reliability (ISSN: 0018-9529), Vol. 58, No 1, March 2009, pp. 193-201.
  128. P. Reviriego, J.A. Maestro, "Study of the Effects of Multibit Error Correction Codes on the Reliability of Memories in the Presence of MBUs", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 9, No 1, March 2009, pp. 31-39.
  129. P. Reviriego, J.A. Maestro, "Efficient Error Detection Codes for Multiple Bit Upset Correction in SRAMs with BICS", ACM Transactions on Design Automation of Electronic Systems (ISSN: 1084-4309), Vol. 14, No 1, January 2009, pp. 18:1-18:10.
  130. J.A. Maestro, P. Reviriego, P. Reyes, O. Ruano, "Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study", Integration, the VLSI Journal (ISSN: 0167-9260), Vol. 42, No 2, January 2009, pp. 128-136.
  131. P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study", Journal of VLSI Signal Processing Systems for Signal Image and Video Technology (ISSN: 0922-5773), Vol. 52, No 3, September 2008, pp. 231-247.
  132. P. Reviriego, J.A. Maestro, O. Ruano, "Efficient Protection Techniques Against SEUs for Adaptive Filters: An Echo Canceller Case Study", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 55, No 3, June 2008, pp. 1700-1707.
  133. P. Reviriego, J.A. Maestro, C. Cervantes, "Reliability Analysis of Memories Suffering Multiple Bit Upsets", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 7, No 4, December 2007, pp. 592-601.
  134. P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "New Protection Techniques against SEUs for Moving Average Filters in a Radiation Environment", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 54, No 4, August 2007, pp. 957-964.

Published Conference Proceedings

  1. L. Aranda, P. Reviriego, J.A. Maestro, "Design Placement Guidelines for Single Event Upset (SEU) Minimization in SRAM-based FPGAs", Design of Circuits and Integrated Systems Conference (DCIS2017), Barcelona (Spain), November 22-24, 2017.
  2. J. Martínez, J.A. Maestro, P. Reviriego, "A Generalized Scheme to Enhance Error Detection in the Instruction Set Architecture", Design of Circuits and Integrated Systems Conference (DCIS2017), Barcelona (Spain), November 22-24, 2017.
  3. M. Atamaner, O. Ergin, M. Ottavi, P. Reviriego, "Detecting Errors in Instructions with Bloom Filters", 30th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2017), Cambridge (UK), October 23-25, 2017.
  4. A. Cóbreces, J. Tabero, A. Regadío, A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "SEU and SEFI protection for DDR3 memories in a Xilinx Zynq-7000 FPGA", 6th IEEE International Conference on Space Mission Challenges for Information Technology (SMC-IT 2017), Alcalá de Henares (Spain), September 27-29, 2017.
  5. L. Aranda, P. Reviriego, J.A. Maestro, "A Fault-Tolerant Implementation of the Median Filter", Proc. of the RADECS 2016 conference, Bremen (Germany), September 19-23, 2016.
  6. R. González-Toral, P. Reviriego, J.A. Maestro, Z. Gao, "A Novel Concurrent Error Detection Technique for the Fast Fourier Transform Implemented in SRAM-based FPGAs", Proc. of the RADECS 2016 conference, Bremen (Germany), September 19-23, 2016.
  7. Z. Gao, P. Reviriego, J.A. Maestro, "Efficient Fault Tolerant Parallel Matrix-Vector Multiplications", Proc. of the IEEE International Online Test Symposium (IOLTS'16), Sant Feliu de Guixols (Spain), July 4-6, 2016, pp. 25-26.
  8. P. Reviriego, J.A. Maestro, S. Pontarelli, M. Bonola, "Improving Cuckoo Filter Performance for High Speed Packet Processing", 25th European Conference on Networks and Communications (EuCNC 2016), Athens (Greece), June 27-30, 2016.
  9. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, "A Method to Protect Bloom Filters from Soft Errors", 28th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015), Amherst, MA (USA), October 12-14, 2015, pp. 80-84.
  10. A. Paschalis, H. Michalik, N. Kranitis, C. López-Ongil, P. Reviriego, "Dependable Reconfigurable Space Systems: Challenges, New Trends and Case Studies", Proc. of the IEEE International Online Test Symposium (IOLTS'14), Playa de Aro (Spain), July 7-9, 2014, pp. 222-227.
  11. G. Yalcin, E. Islek, O. Tozlu, P. Reviriego, A. Cristal, O. Unsal, O. Ergin, "Exploiting a Fast and Simple ECC for Scaling Supply Voltage in Level-1 Caches", Proc. of the IEEE International Online Test Symposium (IOLTS'14), Playa de Aro (Spain), July 7-9, 2014, pp. 1-6.
  12. M. Demirci, P. Reviriego, J.A. Maestro, "Implementing Double Error Correction Orthogonal Latin Squares Codes in Xilinx FPGAs", Proc. of the 3rd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'14), Dresde (Germany), March 27-28, 2014, pp. 48-51.
  13. S. Yegin, B. Karsli, O. Ergin, M. Ottavi, S. Pontarelli, P. Reviriego, "Improving the Reliability of Skewed Caches through ECC based Hashes", Proc. of the 3rd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'14), Dresde (Germany), March 27-28, 2014, pp. 28-31.
  14. P. Reviriego, S. Liu, S. Lee, N.A. Touba, J.A. Maestro, R. Datta, "Implementing Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Squares Codes", 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), New York City (USA), October 2-4, 2013, pp. 167-171.
  15. A.B. Boruzdina, A.V. Ulanova, A.G. Petrov, V.A. Telets, P. Reviriego, J.A. Maestro, "Verification of SRAM MCUs calculation technique for experiment time optimization", Proc. of the RADECS 2013 conference, Oxford (U.K.), September 23-27, 2013, pp. 1-4.
  16. P. Reviriego, S. Liu, S. Lee, J.A. Maestro , "Efficient Error Detection in Double Error Correction Orthogonal Latin Squares Codes", Proc. of the 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'13), Avignon (France), May 30-31, 2013.
  17. P. Reviriego, C. Aryrides, C. Kokkinos, J.A. Maestro, "Enhanced Decoding of Triple Error Correction Reed-Muller Codes to Reduce Silent Data Corruption in Memories", Proc. of the 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'13), Avignon (France), May 30-31, 2013.
  18. A. Sánchez-Macián, P. Reviriego, J.A. Maestro, "Modeling Reliability of Memories Protected with Error Correction Codes with RIIF", Proc. of the RIIF DATE 2013 Workshop, Grenoble (France), March 18-22, 2013.
  19. J.A. Maestro, A. Sánchez-Macián, P. Reviriego, S. Baeg, "Optimizing the Protection of Narrow Values in Memories Protected with Hamming Codes", Proc. of the RADECS 2012 conference, Biarritz (France), September 24-28, 2012.
  20. P. Reviriego, V. Sivaraman, Z. Zhao, J.A. Maestro, A. Vishwanath, A. Sánchez-Macián, C. Russell, "An Energy Consumption Model for Energy Efficient Ethernet Switches", Proc. of the 2012 International Conference on High Performance Computing & Simulation (OPTIM Workshop) (ISBN: 978-1-4673-2362-8), Madrid (Spain), July 2-6, 2012, pp. 98-104.
  21. P. Reviriego, C. Bleakley, J.A. Maestro, "A Novel Concurrent Error Detection Technique for the Fast Fourier Transform", Proc. of the 23nd IET Irish Signals and Systems Conference (ISSC'12), Maynooth (Ireland), June 28-29, 2012.
  22. P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "Low Power embedded DRAM Caches using BCH code Partitioning", Proc. of the IEEE International Online Testing Symposium (IOLTS 2012), Sitges (Spain) (ISBN: 978-1-4673-2084-9), June 27-29, 2012, pp. 79-83.
  23. P. Reviriego, C. Bleakley, J.A. Maestro, "Low Complexity Concurrent Error Detection for Complex Multiplication", Proc. of the 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy (France), June 1, 2012, pp. 33-36.
  24. P. Reviriego, M. Flanagan, J.A. Maestro, "Efficient Multibit Error Correction for Memory Applications Using Euclidean Geometry Codes", Proc. of the RADECS 2011 conference (ISBN: 978-1-4577-0587-8), Sevilla (Spain), September 19-23, 2011, pp. 160-163.
  25. P. Reviriego, J.A. Maestro, I. López-Calle, J.A. de Agapito, "Soft Error Tolerant Infinite Impulse Response Filters Using Reduced Precision Replicas", Proc. of the RADECS 2011 conference (ISBN: 978-1-4577-0587-8), Sevilla (Spain), September 19-23, 2011, pp. 493-496.
  26. I. López-Calle, F.J. Franco, J.A. Agapito, J.G. Izquierdo, P. Reviriego, J.A. Maestro, "TPA laser source for SEE test at UCM", Proc. of the RADECS 2011 conference (ISBN: 978-1-4577-0587-8), Sevilla (Spain), September 19-23, 2011, pp. 454-457.
  27. F.J. Franco, C. Palomar, S. Liu, I. López-Calle, J.A. Maestro, J.A. Agapito, "Defining a strategy to perform life-tests with analog devices", Proc. of the RADECS 2011 conference (ISBN: 978-1-4577-0587-8), Sevilla (Spain), September 19-23, 2011, pp. 92-98.
  28. P. Reviriego, J.A. Maestro, S. Baeg, "Designing Ad-hoc Scrubbing Sequences to Improve Memory Reliability against Soft Errors", Proc. of the Design Automation Conference (DAC'11) (ISBN: 978-1-4503-0636-2), San Diego (USA), 5-9 June 2011, pp. 700-705.
  29. P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance", Proc. of the IFIP/TC6 NETWORKING 2011 Workshop on Sustainable Networking (SUNSET), Valencia (Spain), May 2011, pp. 265-272.
  30. P. Reviriego, K. Christensen, A. Sánchez-Macián, J.A. Maestro, "Using Coordinated Transmission with Energy Efficient Ethernet", Proc. of the IFIP/TC6 NETWORKING 2011 Conference, Valencia (Spain), May 2011, pp. 160-171. [Download NS2 simulation codes here]
  31. O. Ruano, J.A. Maestro, P. Reviriego, "Validation and Optimization of TMR Protections for Circuits in Radiation Environments", Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS'11), Cottbus (Germany), April 13-15, 2011, pp. 399-400.
  32. S.Y. Lee, S. Baeg, P. Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors", Proc. of the IEEE International Integrated Reliability Workshop (IIRW'10), Stanford (USA), October 2010, pp. 114-117.
  33. S. Liu, G. Sorrenti, P. Reviriego, F. Casini, J.A. Maestro, M. Alderighi, "A Fault Tolerant Adaptive Equalizer implemented with Reconfigurable SRAM-based FPGAs", Proc. of the RADECS 2010 conference, Längenfeld (Austria), September 2010.
  34. P. Reviriego, C. Argyrides, J.A. Maestro, D.K. Pradhan, "Enabling Performance versus Reliability Tradeoffs in Memories Using Block Parity", Proc. of the RADECS 2010 conference, Längenfeld (Austria), September 2010.
  35. P. Reviriego, D. Larrabeiti, J.A. Maestro, "Would Energy Efficient Ethernet be effective on 10Gbps Optical Links?", Proc. of the Optical Society of America (OSA) Photonics in Switching meeting, Monterey (USA), July 2010.
  36. P. Reviriego, A. Sánchez-Macián, J.A. Maestro, C. Bleakley, "Increasing the MTU size for Energy Efficiency in Ethernet", Proc. of the 21st IET Irish Signals and Systems Conference (ISSC'10), Cork (Ireland), June 22-24, 2010.
  37. P. Reviriego, D. Larrabeiti, J.A. Maestro, J.A. Hernández, P. Afshar, L. G. Kazovsky, "Energy Efficiency in 10Gbps Ethernet Transceivers: Copper versus Fiber", Proc. of the Optical Fiber Communication Conference and Exposition (OFC/NFOEC'10), San Diego (USA), March 2010.
  38. P. Reviriego, J.A. Maestro, S. Baeg, S. Wen, R. Wong, "Selection of the Optimal Interleaving Distance for Memories Suffering MCUs", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 499-502.
  39. S. Liu, P. Reviriego, J.A. Maestro, "Fault Tolerant FIR Filters Using Hamming Codes", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 484-487.
  40. C. Argyrides, P. Reviriego, D.K. Pradhan, J.A. Maestro, "A Novel Error Correction Technique for Adjacent Errors", Proc. of the RADECS 2009 conference, Bruges (Belgium), September 2009, pp. 480-483.
  41. P. Reviriego, J.A. Maestro, A. O'Donnell, C. Bleakley, "Soft Error Detection and Correction for FFT Based Convolution using Different Block Lengths", Proc. of IEEE International On-Line Testing Symposium (IOLTS'09), Lisbon (Portugal), June 2009, pp. 138-143.
  42. A. O'Donnell, C. Bleakley, P. Reviriego, J.A. Maestro, "Efficient Concurrent Error Detection and Correction of Soft Errors in NTT-based Convolutions", Proc. of the 20th IET Irish Signals and Systems Conference (ISSC'09), Dublin (Ireland), June 2009.
  43. S. Baeg, P. Reviriego, J.A. Maestro, S. Wen, R. Wong, "Analysis of a Multiple Cell Upset Failure Model for Memories", Proc. of the 2009 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'09), Stanford University (USA), March 2009, http://www.selse.org/program.html .
  44. P. Reviriego, J.A. Maestro, "A Technique to Calculate the MBU Distribution of a Memory under Radiation Suffering the Event Accumulation Problem", Proc. of the RADECS 2008 conference, Jyväskylä (Finland), September 2008, pp. 393-396.
  45. O. Ruano, P. Reviriego, J.A. Maestro, "Automatic Insertion of Selective TMR for SEU Mitigation", Proc. of the RADECS 2008 conference, Jyväskylä (Finland), September 2008, pp. 284-287.
  46. J.A. Maestro, P. Reviriego, "Study of the Effects of MBUs on the Reliability of a 150 nm SRAM Device", Proc. of the Design Automation Conference (DAC'08) (ISBN: 978-1-60558-115-6), Anaheim (USA), 8-13 June 2008, pp. 930-935.
  47. O. Ruano, J.A. Maestro, P. Reviriego, "Performance Analysis and Improvements for a Simulation-based Fault Injection Platform", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'08), Cambridge (U.K.), June 2008, pp. 2299-2304.
  48. O. Ruano, P. Reviriego, J.A. Maestro, "A New EDAC Technique against Soft Errors based on Pulse Detectors", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'08), Cambridge (U.K.), June 2008, pp. 2293-2298.
  49. P. Reviriego, P. Reyes, J.A. Maestro, O. Ruano, "System Knowledge-Based Techniques against SEUs for Adaptive Filters", Proc. of the RADECS 2007 conference, Deauville (France), September 2007, pp. 48-52.
  50. O. Ruano, P. Reyes, J.A. Maestro, L. Sterpone, P. Reviriego, "An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques", Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), Kraków (Poland), April 2007, pp. 261-266.
  51. O. Ruano, J.A. Maestro, P. Reyes, P. Reviriego, "A Simulation Platform for the Study of Soft Errors on Signal Processing Circuits through Software Fault Injection", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo (Spain), June 2007, pp. 3316-3321.
  52. P. Reyes, P. Reviriego, J.A. Maestro, O. Ruano, "A New Protection Technique for Finite Impulse Response (FIR) Filters in the Presence of Soft Errors", Proc. of IEEE International Symposium on Industrial Electronics (ISIE'07), Vigo (Spain), June 2007, pp. 3328-3333.
  53. P. Reyes, P. Reviriego, O. Ruano, J.A. Maestro, "Efficient Structures for the Implementation of Moving Average Filters in the Presence of SEUs using System Knowledge", Proc. of the RADECS 2006 conference, Athens (Greece), September 2006, pp. 102-105.

Other Publications

  1. P. Reviriego, J.A. Maestro, "Optimize Energy Efficient Ethernet (IEEE 802.3az) performance in bundled links", EE Times, August 2011, http://www.eetimes.com/design/industrial-control/4218670/Optimize-Energy-Efficient-Ethernet--IEEE-802-3az--performance-in-bundled-links?Ecosystem=communications-design .
  2. P. Reviriego, L. Holst, J.A. Maestro, "On the Expected Longest Length Probe Sequence for Hashing with Separate Chaining", Journal of Discrete Algorithms (ISSN 1570-8667), Vol. 9, No 3, September 2011, pp. 307-312.
  3. P. Reviriego, J.A. Maestro, C.J. Bleakley, "Implications of Energy Efficient Ethernet for Hubs and Switches", International Journal of Communications Networks and Distributed Systems (ISSN 1754-3916), Vol. 6, No. 1, January 2011, pp. 3-11.
  4. P. Reviriego, J.A. Maestro, P. Congdon, "Reduce latency in energy efficient Ethernet switches with early destination lookup”, CommsDesign, April 2010, http://www.commsdesign.com/design_corner/showArticle.jhtml;?articleID=224400657 .
  5. P. López, M. Cid , P. Reviriego, J.A. Maestro, D. Larrabeiti, "Ahorro Energético en Redes Ethernet mediante Adaptación Automática de Velocidad", Proc. of Telecom I+D 2009, Madrid, November 2009.
  6. P. Reviriego, C. Bleakley, J.A. Maestro, "Energy efficiency in Ethernet receivers", CommsDesign, September 2009, http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=220000945 .
  7. O. Ruano, J.A. Maestro, P. Reyes, P. Reviriego, "Plataforma de Simulación y Análisis para el Estudio de los Efectos de la Radiación sobre Circuitos de Comunicaciones", Proc. of Telecom I+D 2006, Madrid, November 2006.

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