Research on Circuits Design for Radiation Environments
The main idea behind our research is to protect digital circuits against the effects of radiation. One of the main effects in the Space
environment is Single Event Upsets (SEUs), which may flip the value of storage elements, for example flip-flops. To deal with SEUs, Triple
Modular Redundancy (TMR) is normally used. This technique replaces each flip-flop with a group of three and some voting logic, so that
the wrong behavior can be corrected. Although it is simple and general, TMR comes at a high cost in terms of circuit area and power
consumption. The baseline of our research is to examine the effects of SEUs at a higher level of abstraction and find more specific
protection techniques with lower delay, area and power overhead.
For example, in a communication system a single error in
the datapath of the reception channel can be acceptable if we are still within the Bit Error Rate (BER) specifications.
Similarly, in a circuit that is doing measurement of some physical signal continuously, it can be acceptable to just detect SEUs
and drop the measurement in which the error occurs if SEUs are unlikely for any given measurement interval. Another way to exploit higher
levels of abstraction is to use the structure of certain circuit implementations to deal with SEUs. One example is Signal Processing
Circuits (like Digital Filters and Fast Fourier Transforms). This approach can result in more efficient circuit implementations in terms
of area and power while maintaining the protection against SEUs. Our current research projects expand the expertise acquired
on stand-alone digital circuits to more complex systems as microprocessors and memories.
We use a wide range of FPGA boards (mainly Xilinx) and CAD software. For ASIC simulation, we are specifically
using (and maintaining) the SEUs Simulation Tool (SST) developed at ESA, as a quick and convenient way to inject soft errors in the design.