ESA ESA - Universidad Antonio de Nebrija
The Group
SST tool
Welcome to the Web site of the Electronic Design and Space Technology group @ Universidad Antonio de Nebrija

In this page, information about the research activity of the group is provided.

In particular, the development work on the Europen Space Agency SST tool can be found.

Research on Circuits Design for Radiation Environments
The main idea behind our research is to protect digital circuits against the effects of radiation. One of the main effects in the Space environment is Single Event Upsets (SEUs), that may flip the value of storage elements, for example flip-flops. To deal with SEUs, Triple Modular Redundancy (TMR) is normally used. This technique replaces each flip-flop with a group of three and some voting logic, so that the wrong behavior can be corrected. Although it is simple and general, TMR comes at a high cost in terms of circuit area and power consumption. In this project, we plan to examine the effects of SEUs at a higher level of abstraction. For example, in a communication system a single error in the datapath of the reception channel can be acceptable if we are still within the Bit Error Rate (BER) specifications. Similarly, in a circuit that is doing measurement of some physical signal continuously, it can be acceptable to just detect SEUs and drop the measurement in which the error occurs if SEUs are unlikely for any given measurement interval. Another way to exploit higher levels of abstraction is to use the structure of certain circuit implementations to deal with SEUs. One example is Signal Processing Circuits (like Digital Filters and Fast Fourier Transforms). This approach can result in more efficient circuit implementations in terms of area and power while maintaining the protection against SEUs.

To be able to develop the previous ideas, we need a platform that allows introducing SEUs in digital circuits and evaluate their effects. Given that we will experiment with different circuits and assess a number of techniques, the ideal solution should be flexible and allow quick evaluation of circuits. We plan to use the SEUs Simulation Tool (SST) developed at ESA which will be enhanced during this project.
   Universidad Antonio de Nebrija.