SST tool
Welcome to the ARIES research center website

ARIES (Aerospace Research and Innovation in Electronic Systems) is a research center integrated in the ecosystem of Nebrija University. This center was founded as an initiative of Nebrija to promote research in the field of fault tolerant electronics for space applications. The positioning and scientific achievements reached in this area by Nebrija University has led to the creation of this center, proving a strong commitment to quality research.

ARIES objectives are:

  • To add value, in the field of digital electronics, to companies and research centers in the space sector and society in general.
  • To perform technology transfer to industry through national and international competitive projects.
  • To contribute to the scientific production by publishing research results in top impact journals.
  • To train doctoral candidates, within the Ph.D. program in Industrial Technologies of Nebrija University, integrating them in the research projects developed at the center, thus producing doctoral theses of the highest quality.
Some facts about ARIES:
  • ARIES is composed of permanent and associate researchers. Permanent researchers are the vast majority of the ARIES staff, who also belong to the School of Engineering faculty of Nebrija University. Currently, ARIES staff includes researchers from five different nationalities, which reflects the international focus of the center.
  • ARIES is based on excellence, with the specific goal of recruiting the best researchers in the field of reliable electronics. ARIES has established a well defined scientific career for researchers, strictly supported in a merit system. For example, in order to belong to the senior researcher category, at least an h-index of 10 is required, among other mandatory merits.
  • ARIES is partly funded by research projects. In this way, the center has an active participation in competitive research projects in both European and national calls. ARIES is present in Horizon 2020 projects and the Spanish National R & D Plan, in the area of space.
  • ARIES is very focused on scientific production through publications in top impact journals in the Journal Citation Report (JCR). Specifically, ARIES has more than 100 scientific papers in JCR journals, along with a significant number of publications in international conferences

Research on Circuits Design for Radiation Environments
The main idea behind our research is to protect digital circuits against the effects of radiation. One of the main effects in the Space environment is Single Event Upsets (SEUs), which may flip the value of storage elements, for example flip-flops. To deal with SEUs, Triple Modular Redundancy (TMR) is normally used. This technique replaces each flip-flop with a group of three and some voting logic, so that the wrong behavior can be corrected. Although it is simple and general, TMR comes at a high cost in terms of circuit area and power consumption. The baseline of our research is to examine the effects of SEUs at a higher level of abstraction and find more specific protection techniques with lower delay, area and power overhead.

For example, in a communication system a single error in the datapath of the reception channel can be acceptable if we are still within the Bit Error Rate (BER) specifications. Similarly, in a circuit that is doing measurement of some physical signal continuously, it can be acceptable to just detect SEUs and drop the measurement in which the error occurs if SEUs are unlikely for any given measurement interval. Another way to exploit higher levels of abstraction is to use the structure of certain circuit implementations to deal with SEUs. One example is Signal Processing Circuits (like Digital Filters and Fast Fourier Transforms). This approach can result in more efficient circuit implementations in terms of area and power while maintaining the protection against SEUs. Our current research projects expand the expertise acquired on stand-alone digital circuits to more complex systems as microprocessors and memories.

We use a wide range of FPGA boards (mainly Xilinx) and CAD software. For ASIC simulation, we are specifically using (and maintaining) the SEUs Simulation Tool (SST) developed at ESA, as a quick and convenient way to inject soft errors in the design.

   Universidad Antonio de Nebrija.